1. Technical Field
This disclosure is related to semiconductor packages and methods of fabricating the same and, more particularly, related to a fan-out type semiconductor package and methods of fabricating the same.
2. Description of Related Art
A major trend in development of the semiconductor field, is to reduce the size of a semiconductor device. As consumption of small-sized computer and mobile electronic device is rapidly increasing, semiconductor packages capable of providing multiple pins in a smaller size, such as a fine pitch ball grid array (FBGA) package or a chip scale package (CSP), are being developed.
Semiconductor packages such as an FBGA package or a CSP have an advantage in having smaller sizes and lighter weights. However, such packages do not provide a reliability equivalent to a conventional plastic package. In addition, the costs of raw materials used during fabrication and the processing costs are relatively high. A micro BGA (μBGA) package has better characteristics compared to the FBGA package or the CSP; however this package is also less reliable and less competitive in cost.
To overcome these shortcomings, a wafer level CSP (WL-CSP) has been developed, which uses redistribution of bonding pads of semiconductor chips on wafer. In a WL-CSP using redistribution, bonding pads on the semiconductor substrate are directly redistributed to larger pads. External connection terminals such as solder balls are disposed on the larger pads.
In such WL-CSP, the size of solder balls are scaled down as the size of semiconductor chips become smaller. As the size of the solder balls decreases, a solder ball layout having finer pitch is required. However, compared to the downsizing of the semiconductor chips by the continuously decreasing design rule, there is limit to an art of making finer solder ball layouts.